Adjustable voltage boundary scan adapter for emulation and test

ABSTRACT

An apparatus for emulating, testing, interrogating, debugging, and programming an integrated circuit is provided. The apparatus has a boundary scan adapter in association with a host computer for accepting a control signal from the host computer, and for generating an intermediate signal for acceptance by the integrated circuit which intermediate signal is compliant with the specifications of the integrated circuit. Also, the apparatus has an interface associated with the integrated circuit for accepting the intermediate signal from the boundary scan adapter. The control signal from the host computer has a magnitude greater than the magnitude of the intermediate signal which intermediate signal is specific to and compliant with the operation of the integrated circuit.

FIELD OF THE INVENTION

The present invention relates to boundary scan interface logic onintegrated circuits and how the defined signal levels are used.Specifically, the present invention relates to integrated circuitsoperating at low voltages with a boundary scan interface, and providingfor the integrated circuit to be emulated, tested, interrogated,debugged, and programmed.

BACKGROUND OF THE INVENTION

The present invention relates to the type of integrated circuits whichoperate at a low voltage level. Typically, such integrated circuits areused in portable communications devices such as cellular telephones andhand held video games.

To reduce the cost of the customer's end product in high volumeproduction, the integrated circuit with a boundary scan interfaceoperates at a low voltage. The boundary scan interface may be, forexample, a microprocessor, a gate array or Digital Signal Processor. Alow voltage may be considered as 1.8 or 2.5 volts DC. Such anarrangement has no logic to interface to the boundary scan interfacewhich operates at a higher voltage, such as for example, +5 volts DC.

If an existing boundary scan adapter were attached to the customer's endproduct, the boundary scan adapter and the customer's end product may bedamaged because of the potential difference of +5 VDC, on one hand, and+1.8 or 2.5 VDC, on the other hand, between the two pieces of logic. Forthe engineer to develop the product safely, a two step process wouldhave to take place. A prototype would need to be designed with specialvoltage logic for boundary scan emulation so the software algorithms forthe integrated circuit could be debugged. And thereafter, the real endproduct must be designed without specialized voltage logic. Such adesigning procedure means the “existing” boundary scan emulator cannotbe used. This approach is time consuming and expensive. Two differentproducts have to be developed, and the final product cannot becompletely debugged and tested.

The referenced type of integrated circuits operate at a voltage lowerthan +3.3 or +5 volts DC, such as for example, 2.5 or 1.8 volts DC.These lower voltages used by the integrated circuit preclude the use ofexisting boundary scan adapters. Existing boundary scan adapters expectto interface with boundary scan logic operating at 3.3 or 5.0 volts DC.This means existing boundary scan adapters cannot be used to test,interrogate, debug software algorithms, and program non-volatilememories in the system.

It is, therefore, a feature of the present invention to provide anadjustable voltage boundary scan adapter, used for emulation and test,that can operate with integrated circuit boards having low voltages.

A feature of the present invention is to provide an adjustable voltageboundary scan adapter, when used for emulation and test, that does notrequire additional support circuitry around the integrated circuit.

Another feature of the present invention is to provide an adjustablevoltage boundary scan adapter that can be have its interface logicvoltage levels adjusted to match the voltage levels present on theintegrated circuit.

Another feature of the present invention is to provide an adjustablevoltage boundary scan adapter to allow low voltage integrated circuitswith a boundary scan interface to be tested.

Another feature of the present invention is to provide an adjustablevoltage boundary scan adapter to allow low voltage integrated circuitswith a boundary scan interface to be interrogated.

Yet another feature of the invention is to provide an adjustable voltageboundary scan adapter to allow low voltage integrated circuits with aboundary scan interface to debug software algorithms.

Still another feature of the present invention is utilizing anadjustable voltage boundary scan adapter to allow low voltage integratedcircuits with a boundary scan interface to program non-volatile memoryin the system without special logic in the system.

Additional features and advantages of the invention will be set forth inpart in the description which follows, and in part will become apparentfrom the description, or may be learned by practice of the invention.The features and advantages of the invention may be realized by means ofthe combinations and steps particularly pointed out in the appendedclaims.

SUMMARY OF THE INVENTION

To achieve the foregoing objects, features, and advantages and inaccordance with the purpose of the invention as embodied and broadlydescribed herein, an adjustable voltage boundary scan adapter that canbe used for emulation and test is provided. The purpose of theadjustable voltage boundary scan adapter of the present invention is toallow low voltage integrated circuits with a boundary scan interface tobe tested, interrogated, software algorithms debugged, and non-volatilememory in the system programmed without special logic in the system.

The adjustable voltage boundary scan adapter of the present inventionallows the user to select the voltage level at which an integratedcircuit boundary scan interface will operate. In one embodiment, thisselection is done with a rotary selection switch on the adjustablevoltage boundary scan adapter. Other embodiments could include makingthis selection with a potentiometer or physical jumper connection. Theadjustable voltage boundary scan adapter has a programmable integratedcircuit which reads the switch setting selections and adjusts itsboundary scan signal levels accordingly.

In one embodiment, an apparatus for emulating, testing, interrogating,debugging, and programming an integrated circuit is provided comprisinga boundary scan adapter and an interface associated with the integratedcircuit. The boundary scan adapter is in association with a hostcomputer for accepting a control signal from the host computer, and forgenerating an intermediate signal for acceptance by the integratedcircuit. The intermediate signal is compliant with the specifications ofthe integrated circuit. The interface associated with the integratedcircuit is for accepting the intermediate signal from the boundary scanadapter. The control signal from the host computer has a magnitudegreater than the magnitude of the intermediate signal which intermediatesignal is specific to and compliant with the operation of the integratedcircuit.

In another embodiment, an apparatus for emulating, testing,interrogating, debugging, and programming an integrated circuit isprovided comprising a host computer, a boundary scan adapter and aninterface associated with the integrated circuit. The host computergenerates a control signal for the apparatus. The boundary scan adapteris in association with the host computer for accepting the controlsignal from the host computer, and for generating an intermediate signalfor acceptance by the integrated circuit. The intermediate signal iscompliant with the specifications of the integrated circuit. Theboundary scan adapter comprises a controller for accepting the controlsignal from the host computer and for generating a driver signal, thedriver signal being at least one of equal to or not equal to the controlsignal, and a pin driver/receiver for receiving the driver signal fromthe controller and for generating an intermediate signal for acceptanceby the integrated circuit which intermediate signal is compliant withthe specifications of the integrated circuit. The interface associatedwith the integrated circuit accepts the intermediate signal from theboundary scan adapter. The control signal from the host computer has amagnitude greater than the magnitude of the intermediate signal whichintermediate signal is specific to and compliant with the operation ofthe integrated circuit.

The following sequence is an example used by the adjustable voltageboundary scan adapter to determine the voltage at which to set itsboundary scan signal levels.

1. When the cable from the adjustable voltage boundary scan adapter isplugged into a logic card resident in a personal computer and power isapplied to the adjustable voltage boundary scan adapter, LEDs (lightemitting diodes) will flash for a specified period of time.

2. A multi-position rotary switch is read by a microprocessor and thevoltages are set per an appropriate table of values.

3. The presence/power detect (PD) signal is monitored until its voltagelevel exceeds the Power Detect Input Threshold. An LED under the controlof a microprocessor will flash until this condition is met.

4. When the integrated circuit power is detected the JTAG outputs of theadjustable voltage boundary scan adapter will be enabled.

5. Once the JTAG outputs are enabled, the test-reset-input (TRST) lineis monitored and the microprocessor will flash an LED until the TRSTline is taken high by the software driver of the adapter in the personalcomputer. Once the TRST line is taken high, EMU0 will be released fromits Wait-In-Reset value and return to a tri-state condition. The LEDwill then turn off.

6. When target power is detected and TRST is high and the LEDs willreflect the rotary switch setting.

7. The PD and TRST pins are monitored continuously. If either signaldrops below its high threshold then the power detection sequence willstart over at step #2.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings which are incorporated in and constitute apart of the specification, illustrate a preferred embodiment of theinvention and together with the general description of the inventiongiven above and the detailed description of the preferred embodimentgiven below, serve to explain the principles of the invention.

FIG. 1A is an illustration of the system of the present invention.

FIG. 1B is a block diagram of the system illustrated in FIG. 1A.

FIG. 1C is an illustration of the relationship of the boundary scanapparatus with the integrated circuit.

FIG. 2 is an illustration of another embodiment of the softwaredevelopment system of the present invention.

FIG. 3A is an illustration of one embodiment of a generic pindriver/receiver.

FIG. 3B is an illustration of another embodiment of a pindriver/receiver.

FIG. 4A illustrates a generic pin receiver.

FIG. 4B is another embodiment of a pin receiver.

FIG. 4C is yet another embodiment of a pin receiver.

FIG. 5 is another embodiment of a master control block.

FIG. 6 illustrate still another embodiment of the master control block.

FIG. 7 illustrates a more complex version of the embodiment of thepresent invention.

FIG. 8 illustrates yet another embodiment of the present invention.

The above general description and the following detailed description aremerely illustrative of the generic invention, and additional modes,advantages, and particulars of this invention will be readily suggestedto those skilled in the art without departing from the spirit and scopeof the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention as described in the accompanying drawings.

The present invention relates to the boundary scan interface logic onintegrated circuits defined in accordance with the IEEE 1149.1 standardand how the defined signal levels are used. With the boundary scaninterface on the integrated circuit, a boundary scan adapter, and theappropriate software, the integrated circuit can be controlled. Withthis software controlling the boundary scan adaptor the integratedcircuit can be emulated, tested, interrogated, software algorithms canbe debugged, and non-volatile memory in the system can be programmed.

FIG. 1A is an illustration of the system 10 of the present invention.The system 10 comprises a host computer 12 with software connected tothe boundary scan adapter 100 of the present invention. The boundaryscan adapter 100 is connected to an integrated circuit 14. The hostcomputer 12 is connected to the boundary scan adapter 100 by a conductorcable 16. The boundary scan adapter 100 is connected to the integratedcircuit by a cable 18 and JTAG connector.

FIG. 1B is a block diagram of the system 10 illustrated in FIG. 1A. FIG.1B illustrates the host computer 12 with software being connected viathe conductor cable 16 to the boundary scan adapter 100. The boundaryscan 100 is connected to the integrated circuit 14 via the JTAGconnector 18.

FIG. 1C is an illustration of the relationship of the boundary scanapparatus 100 with the integrated circuit 12. A cable 16 providescommunication between the host computer (not shown) and the boundaryscan apparatus 100. The cable 16 has an input line 102 and from the hostcomputer to the boundary scan apparatus 100, and an output line 108 fromthe boundary scan apparatus 100 to the host computer. Similarly, theconductor cable 18 provides communication between the boundary scanapparatus 100 and the integrated circuit 12. The conductor cable 18 hasan input line 104 from the boundary scan apparatus 100 to the integratedcircuit 12, and an output line 106 from the integrated circuit 12 to theboundary scan apparatus 100.

The signal A₁ is a data stream from the host computer to the boundaryscan apparatus 100. Typical voltage levels for the data stream A₁ arefrom 0 to 5 volts, or TTL compatible. The data stream B₁ from theboundary scan apparatus 100 to the host computer is also typicallybetween 0 and 5 volts, or TTL compatible. The data stream A₂ from theboundary scan apparatus 100 to the integrated circuit 12 is carried bythe conductor 104 in the cable 18. The data stream A₂ has voltage levelsthat are variable. Also, the data stream A₂ is required not to exceedthe specifications for the integrated circuit 12. Typically, the voltagelevels required by the data stream A₂ in practicing the presentinvention are from 0 volts to a maximum of approximately 3.3 volts.Typically, the 0 volts is for the −V signal and the higher levelvoltage, for example the 3.3 volts, is for the +V signal. The digitaldata stream B₂ is provided as an output from the integrated circuit 12to be accepted by the boundary scan apparatus 100. The digital datastream B₂ is carried by the conductor 106 of the cable 18. The voltagelevels associated with the digital data stream B₂ are set and determinedby the voltage requirements of the integrated circuit 12. The voltagelevels for the digital data stream B₂ are generally between 0 volts and5 volts. The 0 volt level is associated with the −V signal and thehigher, for example 5 volt signal, is associated with the +V signal.

The boundary scan apparatus 100 provides a unique method of convertingthe digital data stream A₁ from the host computer to the apparatus 100to a different voltage level, digital data stream A₂ for acceptance by aparticular integrated circuit 12. Similarly, the adjustable voltageboundary scan adapter of the present invention provides a unique way ofconverting the voltage levels B₂ from the particular integrated circuit12 to a voltage level B₁ which is usable by the host computer.Typically, the digital data streams between the host computer and theboundary scan apparatus 100 are fixed by the host computer. It isimportant to note that the digital data streams between the boundaryscan apparatus 100 and the integrated circuit 12 are variable. Thevariable data streams A₂, B₂ are set by the integrated circuit 12 or“target” device. The digital data streams between the boundary scanapparatus 100 and the integrated circuit 12 are required at specificlevels based on the technology of the integrated circuit 12.

FIG. 2 is an illustration of another embodiment of a softwaredevelopment system 200 of the present invention. The softwaredevelopment system 200 comprises a master control block 201 and a pindriver/receiver 203. The signal A₁ is input through a line 202 into amaster control 201. The signal A₁ is a digital data stream form the hostcomputer. Typical voltages for data stream A₁ are from 0 to 5 volts, orTTL compatible. The digital data stream B₁ from the master control block201 to the host computer is transferred along line 208. The digital datastream B₁ has typical voltages from 0 to 5 volts, or TTL compatible. Thedata stream from the master control block 201 to the pin driver/receiver203 are implementation or application specific. The data stream A₃ may,or may not, be equal to A₁ or A_(e). The data stream B₃ from the pindriver/receiver 203 to the master control block 201 is the conversesignal of data stream A₃, but is in the reverse direction. Typically,the amplitude or levels of the data streams A₃ and B₃ are approximatelythe same. The data stream A₂ from the pin driver/receiver 203 to theintegrated circuit 12 are variable and can not exceed the specificationsfor the integrated circuit 12. The levels of the data stream A₂ varygenerally from 0 to approximately 3.3 volts for the −V value and the +Vvalue, respectively. The digital data stream B₂ from the integratedcircuit 12 to the pin driver/receiver 203 are variable and set by thevoltage requirements of the integrated circuit 12. The levels of thedata stream B₂ are generally over the values of −V and up to 5 volts forthe +V value.

The connections 212, 214, 216 and 218 provide specific controlcharacteristics for the system 200 of the present invention. The voltagesupply/level V₁ is for the signal output A₂. The voltage supply/level V₁sets the voltage of A₂. The voltage threshold V₂ is for the signal inputB₂ from the integrated circuit 12 to the pin driver/receiver 203. Thevoltage threshold V₂ sets the threshold voltage for the inputs B₁. Thevoltage threshold V₃ is for sensing the integrated circuit voltagelevel, V_(cc). The voltage threshold V₃ can be used to determine whenpower is applied to the integrated circuit or for automatic sensing ofthe integrated circuit voltage level V_(cc). The voltage feedback V₄from the voltage supply level V₁, the voltage threshold V₂ and thevoltage threshold V₃ is to provide a closed loop system.

The master control block 201 has various functions. The master controlblock 201 formats the data stream A₁ into an internal voltage level A₃format. The data stream A₁ can be parallel, serial, or some higher levelcompound format. The data stream A₃ is a 1-to-1 representation of thedata stream A₂, except for the internal voltage levels. Further, themaster control block 201 provides a reverse function for the return datastreams B₂, B₂, and B₃. The master control block 201 generates theappropriate voltage levels for the voltage supply/level V₁, the voltagethreshold V₂ for the signal input B₂, and the voltage threshold V₃ forthe sensing of the integrated circuit voltage level. Also, the mastercontrol block 201 uses the feedback voltage V₄ to create a closed loopsystem. The closed loop system protection from over-voltage orunder-voltage conditions at the integrated circuit 12. Controlimplantation from the host computer, user or other input device isprovided to the master control block 201. The master control block 201uses the information from the host computer, user or other input deviceto offset voltage discrepancies at the voltage supply/level V₁, thevoltage threshold V₂ or the voltage threshold V₃.

The pin driver/receiver 203 also has several functions. The pindriver/receiver 203 converts the data stream A₃ from an internal fixedvoltage level to the voltage level of the integrated circuit 12 based onthe voltage supply/level V₁. Also, the pin driver/receiver 203 convertsthe data stream B₂ from the integrated circuit voltage level to the datastream B₃ voltage level based on the threshold voltage B₂. The pindriver/receiver 203 generates a target power on/off indicator based onthe threshold voltage V₃. Further, the pin driver/receiver 203 createsthe feedback information V₄ on the line 218 based upon the voltages V₁,V₂ and V₃ and the data streams A₂ and A₃.

FIG. 3A is an illustration of a generic pin driver/receiver 203A. Thegeneric pin driver/receiver 203A has a data stream A₃ as an input signalsource. The resulting output driver signal A₂ is created. A voltagesource V₁+ sets the upper voltage level of A₂ which can be indicated asA_(2(VOH)) . The voltage level V₁− sets the lower voltage level of A₂ orA_(2(VOL)). By adjusting the voltage levels V₁+, V₁−, the resulting A₂can swing between the voltage levels V₁+ and V₁−.

FIG. 3B is an illustration of an inexpensive pin driver/receiver 203Busing off-the-shelve components. The voltage V₁− is set to 0 volts. Thevoltage V₁+ is programmed to match the input voltage requirements of theintegrated circuit 12 or data stream A₂. Thus, the signal A₃ drives theenable pin of the gate G₁. When A₃ is high, the gate G₁ is “off” and thevoltage level A₂ is equal to the voltage V₁+. When A₃ is low, the gateG₁ is “on” and the voltage A₂ is equal the voltage V₁−. The resistor R₁provides a current limit for the voltage V₁+. The value of the resistorR₁ is chosen to match the requirements of the gate G₁. The resistor R₂is optional. The resistor R₂ can be used to effect the impedance of thedata stream or signal A₂. The simplicity and cost of the pindriver/receiver 203B is an important feature. At about 15 cents peroutput pin, you get variable voltage for most common integrated circuitfamilies whose levels range from 1.0 to 5.0 volts. The value of V₁+ mayalso have infinite adjustments within this range.

FIG. 4A illustrates a generic pin receiver 203C. The generic pinreceiver 203C has the data stream V₂ input from the integrated circuit12 or target. The voltage V₂ sets the output/input switch threshold B₂.The data stream B₃ is the resulting signal. The signal B₃ has a levelthat matches that of the master control block 201. The logic “0/1” stateof the signal B₂ can be set by the voltage applied to V₂. When the levelon B₂ exceeds the level on V₂, then B₂ is considered a “1” and thecorresponding level on B₃ is set to “1.” When the level on B₂ fallsbelow V₂, then B₂ is considered a “0” and the corresponding level on B₃is set to “0.” The voltage associated with the V+/V− relationship setsthe overall range of B₂ and B₃. By controlling the voltage of V₂, the“0/1” level of B₂ can be varied. The level on B₂ is independent of theA₂ levels. Thus, the voltage V₂ may be set above or below B₂ associatedwith the integrated circuit 12. The typical “0/1” level to provideadditional noise immunity is a noisy or lossy environment.

FIG. 4B is a specific implementation of a pin receiver 203D. Such aspecific embodiment provides that the voltage V+ is equal to +5 voltsand the voltage V− is equal to 0. The embodiment with the pin receiver203D provides for a B₂ range of 0 to 5 volts.

FIG. 4C illustrates yet another embodiment of a pin receiver 203E. Thepin receiver 203E provides an integrated circuit power detect device. Bysetting the value of voltage V₃, the present invention can detect whenthe integrated circuit 12 is “on,” “off,” or in a “brown out” condition.Such condition information is generally necessary as feedback to controlthe signals A₃, B₃, V₁, V₂, A₂ and A₃. For example, the most obviouscontrol would be to “disable” output drivers A₂ in the case of anintegrated circuit “off” or “brown out” condition. Such control wouldhelp prevent latch up of voltage back driving into the integratedcircuit.

FIG. 5 is another embodiment of a master control block 501. The mastercontrol block 501 comprises a digital processing member 502 and ananalog member 504. The analog member 504 comprises a digital to analogconverter 508 and an analog to digital converter 506.

The digital processing member 502 sends CMDS/data to thedigital-to-analog converter 508 to generate the necessary voltage levelson V₁, V₂, V₃, Also, the digital processing member 502 reads the levelson the V₄ inputs as digital data. The V₄ inputs represent the feedbackpath for V₁, V₂, V₃, A₃ and B₃.

The digital processing member 502 provides overall control for theapparatus of the present invention. The digital processing member may beas simple as a bank of switches or as complicated as a fullmicro-processor/micro-computer control.

FIG. 6 illustrates another embodiment of the master control block 600.In a simple serial stream from the host computer, signal A₁ passesthrough to signal A₃. Similarly, the signal B₃ passes through to signalB₁. Thus, the data-in value is equal to the data-out value. No datavalue formatting is required. The V₁-V₃ voltage levels are set by valueson the digital to analog converter 608. Alternately, the V₁-V₃ voltagelevels may be set by a device as simple as a resistor network. Thevoltage level V₄ may only represent the presence or the absence of poweron the integrated circuit. In the event of no power on the integratedcircuit, the A₃/B₁ signal may be driven to “0” volts for safety reasons.

FIG. 7 illustrates a more complex version of an embodiment of anadjustable voltage boundary scan adapter of the present invention. Thesignal A₂, B₁ present high level commands and data. The micro-processor702 processes the commands and data. The result of the processing of themicro-processor 702 may be sent or transferred to a particular test oremulation sequence to the integrated circuit 12. Alternately, the resultof the micro-processor 702 may be to adjust the voltage level on V₁, V₂,V₃. When utilizing the micro-processor 702, the actions on the feedbackpath can become complex. For example, all the leads V₁, V_(2,), V₃ maybe determined by voltage levels on the integrated circuit supply. If theintegrated circuit power turns “off” or “browns out,” themicro-processor 702 may respond by setting all the digital to analogconverter outputs to “0” volts. The addition of a micro-processor 702creates an overall smarter system with respect to the present invention.The voltage levels can be finely tuned to compensate for noise, drift,lossy lines, etc. It also enables the present invention to implementactions based on integrated circuit events or internal events. Typicalmicro-processor actions which are available when using the presentinvention are to set V₁, V₂, V₃, based on integrated circuit powersupply requirements; continually monitoring the integrated circuit powerlevel looking for a loss of integrated circuit power; with respect tointegrated circuit power loss, reprogramming the digital to analogconverters to levels which protect the integrated circuit from damage;setting levels on V₁, V₂, V₃, independent of integrated circuit powersuch that the integrated circuit power seen by the boundary scanapparatus of the present invention may not represent the true integratedcircuit power; and making adjustments in V₁, V₂, V₃, over time if driftcompensation is required.

FIG. 8 illustrates yet another embodiment of the present invention. Witha modified integrated circuit 12A. The modified integrated circuit 12Ahas a test emulation interface 12B and an integrated “core” function12C. The integrated circuit 12A has an integrated circuit as simple asan SSI logic gate or as complex as a RISC or DSP processor. As changesin integrated circuit technology occur, the integrated circuits willoperate at lower and lower voltages. Today, typical integrated circuitshave 5 volt, 3.3 volt and 2.5 volt input output interfaces. Futuredevices will continue to reduce the voltage of the input outputinterfaces. It is expected that future devices will reduce the inputoutput interfaces of the integrated circuits to 1.8 volts, 1.5 volts and1.0 volts. With such a wide variety of voltage interfaces, atest/emulation interface is required to support the full range ofinterface voltages.

Additional advantages and modification will readily occur to thoseskilled in the art. The invention in its broader aspects is thereforenot limited to the specific details, representative apparatus, and theillustrative examples shown and described herein. Accordingly, thedepartures may be made from the details without departing from thespirit or scope of the disclosed general inventive concept.

1-12. (Cancelled).
 13. An apparatus for emulating, testing,interrogating, debugging, and/or programming an integrated circuit anintegrated circuit boundary scan interface comprising digital and analogmeans for converting a digital data stream from an input device to avariable voltage level for acceptance by an integrated circuit includingmeans for selecting a voltage threshold for sensing the voltage level ofthe integrated circuit boundary scan interface and for converting thereturn data stream from the integrated circuit to a voltage level usableby the input device.
 14. The apparatus of claim 13 wherein said dataconverting means further comprises means for selecting a voltagethreshold for sensing the voltage level of the integrated circuitboundary scan interface.
 15. The apparatus of claim 14 wherein said dataconverting means further comprises means for monitoring the voltagelevel of the integrated circuit boundary scan interface.
 16. Theapparatus of claim 15 wherein said data converting means furthercomprises means for infinitely adjusting voltage levels based on thevoltage level of the integrated circuit boundary scan interface.
 17. Theapparatus of claim 13 wherein the data converting means furthercomprises means for infinitely adjusting voltage levels based oncommands from an input device.
 18. The apparatus of claim 13 wherein thedata converting means further comprises means for adjusting the voltagelevels to protect the integrated circuit boundary scan interface fromdamage in the event of power loss.